CMOS VLSI Design: A Circuits And Systems Perspe...
The book presents a comprehensive introduction to custom VLSI design in the complementary MOS (CMOS) technologies and contains a large number of practical design examples. Topics discussed include CMOS circuits, MOS transistor theory, CMOS processing technology, circuit characterization and performance estimation, and CMOS circuit and logic design. The discussion also covers structured design and testing, symbolic layout systems, and CMOS subsystem design.
CMOS VLSI Design: A Circuits and Systems Perspe...
At the circuit/system level, asynchronous design methods have been drawing continued interest from the research community over the past few decades due to several inherent advantages such as low noise (Paver et al. 1998) and almost nil electro-magnetic interference (Bouesse et al. 2004), greater modularity (van Kees Berkel et al. 1999), capacity to withstand process, temperature, and parametric variations (Kulikowski et al. 2008; Chang et al. 2010), consumption of power only when and where active (van Kees Berkel et al. 1999; Akgun et al. 2010), and being self-checking (David et al. 1995). Low noise and electro-magnetic compatibility imply that asynchronous circuits are inherently resistant to side channel attacks (Yu et al. 2003; Sokolov et al. 2005) and are therefore preferable for secure environments demanded in cyber physical systems, banking and financial applications, and other consumer and industrial applications. Modularity, also known as design reusability, and the ability to tolerate process, temperature and parametric variations signifies that asynchronous circuits are well placed to cope with statistical timing analysis and reliability issues whilst delivering a good average case performance (Sparsø and Furber 2001). Due to power consumption only on demand, depending on when and where required, asynchronous circuits form a natural choice for low power VLSI designs where complimentary design strategies such as multiple supplies, multiple thresholds, and dynamic voltage and/or frequency scaling may be employed to leverage the maximum benefits from an asynchronous design.
While there exists many classes of asynchronous circuits/systems (Sparsø and Furber 2001; Myers 2001), relative-timing (Stevens et al. 2003) was proposed and suggested to be a very efficient asynchronous design style which can aggressively optimize area, delay, and power parameters much more than any other asynchronous design method. This was validated through the relative-timed design of an asynchronous instruction length decoder in (Stevens et al. 2003). However, design metric optimizations are achieved by relative-timed designs at the expense of trading off robustness, i.e., by incorporating certain timing assumptions. However, it should be noted that timing assumptions are implicit in robust asynchronous design methods such as isochronic forks (Martin 1990; Martin and Prakash 2008) in quasi-delay-insensitive designs (Toms 2006; Balasubramanian 2010), which form the weakest compromise to delay-insensitivity (van Berkel 1992), and zero or negligible wire delays in speed-independent designs (Beerel and Meng 1992; Kondratyev et al. 1994; Keller et al. 2009), while timing assumptions are made explicit in the case of relative-timing to optimize the design metrics. 041b061a72